Shallow trench isolation void detecting method and structure for the same

ABSTRACT

Disclosed is a. method for detecting STI void of a semiconductor wafer. The method of the present invention comprises steps of assigning a detecting area in a predetermined region of the wafer; forming active areas and gate strips crossing the active areas by the process synchronized with that for other regions of the wafer. Dielectric material is filled between the active areas. The adjacent portion between the active areas reaches a predetermined length at least. The electrical value of the gate strips is measured to determine whether there is any void in the dielectric filled between the active areas, thereby to derive whether there is any void generated in the STI between the active areas of the other regions of the wafer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device process, morespecifically, to a method for detecting if there is any void in STI.

2. Description of the Prior Art

In the process for semiconductor devices getting more and more compact,shallow trench isolation (STI) is used to separate active areas 10 forforming respective elements. STI is formed between active areas 10 andis filled with dielectric 12, which can be oxide such as silicon oxide.However, a void 13 is likely to be generated in the step of filling withthe dielectric 12, as shown in FIG. 1.

In DRAM process, such a condition also happens. With reference to FIG.2, which is a schematic top view of a gate region structure of a DRAM,reference number 20 indicates an active area, 21 indicates a gate line,24 indicates a deep trench. As shown in the drawing, the adjacentportion between the active areas is short. Reference number 23 indicatesa void formed in the dielectric filled in the STI between the activeareas 20. The existence of the void 23 may influence the electricperformance of the semiconductor structure. However, such a void is verysmall and is hardly found during the process. Usually, the existence ofthe void only can be found in the electric testing, which is performedafter the wafer is finished, cut into chips and packed. Accordingly, awaste of process is generated.

Therefore, there is a need for a solution to overcome the problemsstated above. The present invention satisfies such a need.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a STI void detectingmethod for semiconductor wafers. The method of the present invention canfind in time whether there is any void formed in STI, so that thedefective products can be found in the early stage, thereby reducing thewaste of the cost and working hours.

Another objective of the present invention is to provide a STI voiddetecting region structure for semiconductor wafers. By forming andtesting the testing region structure of the present invention, whetherthere is any void formed in STI can be found in time.

According to an aspect of the present invention, a shallow trenchisolation void detecting method for a semiconductor wafer comprisessteps of assigning a testing region in a predetermined region of thesemiconductor wafer; forming active areas and gate lines inter with theactive areas in said detecting region by a synchronous process for otherregions, filling a trench between the active areas with dielectric, theadjacent portion between the active areas having at least apredetermined length; and detecting the electric values of the gatelines to determine whether there is a void formed in the dielectricfilled in the trench between the active areas.

According to another aspect of the present invention, a testing regionstructure for semiconductor wafer STI void detecting is formed on thewafer by a process synchronizing for other portions of the wafer. Thetesting region structure comprises a plurality of active areas, trenchesbetween the active areas being filled with dielectric, and the portionsof the active areas adjacent to each other having at least apredetermined length; and a plurality of gate lines inter with theactive areas.

BRIEF DESCRIPTION OF THE DRAWINGS

The following drawings are only for illustrating the mutualrelationships between the respective portions and are not drawnaccording to practical dimensions and ratios. In addition, the likereference numbers indicate the similar elements.

FIG. 1 shows a schematic sectional diagram illustrating a void formed ina STI of a semiconductor device;

FIG. 2 is a schematic top view showing the arrangement of the activeareas and gate lines of a semiconductor device in prior art; and

FIG. 3 is a schematic top view showing the arrangement of the activeareas and gate lines of a semiconductor device in accordance with anembodiment of the present invention.

DETIALED DESCRIPTION OF THE PREFERRED EMBODIMENT

An embodiment of the present invention will be described in detail withreference to the accompanying drawings.

According to an embodiment of the present invention, at predeterminedlocations on the wafer, preferably the cut lines portion, testingregions comprising active areas and gate lines are produced by thesynchronous process for other portions of the wafer.

As shown in FIG. 3, the sections of active areas 30 in the testingregion are formed as long strips. Accordingly, the active areas 30 areadjacent to each other. Shallow trenches formed between the active areas30 are filled with dielectric 32 by the process synchronous with otherportions of the wafer. As shown, in the present embodiment, the activeareas 30 are preferably formed as parallel strips. Since the length ofthe portions of two active areas 30 adjacent to each other is very long,if there is a void 33 formed in the dielectric 32, the void 33 will be along void. Gate lines 31′ in the testing region are arranged at aninterval the same as the gate lines in other non-testing regions. Asshown, since the section of the void 33 is long, the void 33 crosses atleast two gate lines 31′. Accordingly, for example, it is easy to detectwhether there is a void existing by measuring the potentials of the gatelines 31′ in the testing region.

According to the present embodiment, for the sake of convenience ofmeasuring, the gate 31 can be formed as a comb-shaped gate. That is, theodd gate lines connected together, while the even gate lines connectedtogether, thereby forming a dual-comb structure. Then the potential of aplurality of gate lines can be measured at a time.

The testing region is produced synchronously with other regions of thewafer. Accordingly, if a void is detected in the testing region, it canbe determined that there are voids formed in other portions of thewafer. Then the detective products can be found and eliminated at anearly stage, but not the stage after the wafer is cut into chips andpacked. Thus, unnecessary working process is avoided, and therefore theworking hours and cost are reduced.

While the embodiment of the present invention is illustrated anddescribed, various modifications and alterations can be made by personsskilled in this art. The embodiment of the present invention istherefore described in an illustrative but not restrictive sense. It isintended that the present invention may not be limited to the particularforms as illustrated, and that all modifications and alterations whichmaintain the spirit and realm of the present invention are within thescope as defined in the appended claims.

1. A method for detecting STI void of semiconductor wafer, comprisingsteps of assigning a test region in a predetermined region of the wafer;forming active areas, trenches between the active areas and gate linesintersecting with tthe active areas, said trenches being filled withdielectric, and said active areas having their adjacent portion reachingat least a predetermined length; and measuring the electric values ofsaid gate lines to determine whether there is a void formed in thetrench.
 2. The method as claimed in claim 1, wherein said active areasin the testing region are formed as parallel strips.
 3. The method asclaimed in claim 1, wherein odd ones of said gate lines are connectedtogether, while even ones of the gate lines are connected together, soas to form a dual-comb structure.
 4. The method as claimed in claim 3,wherein said measuring step is to measure the potentials of the combstructure of the odd gate lines and the comb structure of the even gatelines.
 5. The method as claimed in claim 1, wherein the testing regionis formed on a predetermined cutting line of the wafer.
 6. A testingregion structure for STI void detection of semiconductor wafer, saidtest region structure being formed on the wafer by a process synchronouswith other portions of the wafer, said structure comprising: a pluralityof active areas, the adjacent portion between two active areas reachingat least a predetermined length; a plurality of trenches formed betweenthe active areas and being filled with dielectric; and a plurality ofgate lines intersecting with said active areas.
 7. The structure asclaimed in claim 6, wherein said active areas in the testing region areformed as parallel strips.
 8. The structure as claimed in claim 6,wherein the odd ones of the gate lines are connected together, while theeven ones of the gate lines are connected together, so as to constitutea dual-comb structure.
 9. The structure as claimed in claim 6, whereinthe testing region structure is formed on a predetermined cutting lineof the wafer.